1. Field of the Invention
The present invention relates to an improved structure of an image processing system and particularly relates to connections of common buses between a plurality of image memories and data processors which achieve high speed processings and can have general-purpose utilities.
2. Background of the Art
A previously proposed image processing system will be described below.
A common bus including two (X and Y) address bus lines and three data bus lines is connected to a plurality of image memories (VRAMs). A processor element is connected to the common bus for carrying out predetermined calculations for data read from one or the plurality of the image memories via the data bus line(s) and for writing (storing) a result of calculations into one of the other image memories. In addition, output buffers are connected between each output end of the image memories and processor element and data bus lines. Furthermore, an address controller for outputting address data to the respective image memories is connected to the address bus lines. The address controller controls the addresses of the image memories to scan them for each frame. A controller is provided to control entirely the processor element, address controller, and so on. A VRAM (Video Random Access Memory) controller controls the read and/or write of the respective image memories (VRAMs).
For example, in a processing case where the image data of the image memories are added by the processor element and the added image data is written in one of the other image memories, the data in the corresponding image memories inputted from the data bus lines are added in the processor element. Thereafter, its result is inputted into the data bus and the output data of the processor element may be written into the corresponding image memory. At this time, addresses of the image memories are scanned by means of the address controller for each frame (each image screen).
Such an image processing system as described above is exemplified by a Japanese Patent Application Publication (Unexamined) No. sho 61-153774 published on July 12, 1986.
In such a previously proposed image processing system, the addresses of the image memories are inputted only via the common bus (specifically address bus lines) and data to be processed by the processor element is inputted only via the common bus (specifically data bus lines).
Therefore, such processings as those required to execute calculations of the addresses of the image memories (for example, affine transformations) cannot be executed in the previously proposed image processing system. In addition, simultaneous executions of different processings cannot be carried out due to lack in flexibility of the structure of connections to the common bus as described above.
Furthermore, even if the installed number of processor elements and image memories is desired to be increased (extension of the system components) and the number of buses (bus lines) is increased, the previously proposed image processing system has less flexibility and less general-purpose utilities due to limitations of connections to the buses so that the high-speed and cost effective processings cannot be made.